| The disassembler objconv has now been updated with support for the forthcoming Intel "Many Integrated Core" (MIC) coprocessor code named Knights Corner. See Knights Corner Instruction Set Reference.
This instruction set extends the size of vector registers from 128-bits xmm registers and 256-bits ymm registers to 512-bits zmm registers. The number of vector registers is extended to 32 registers named zmm0 - zmm31 in 64-bit mode. The number of vector registers in 32-bit mode has not been not clarified, but it looks like only zmm0 - zmm7 are available in 32-bit mode for technical reasons. There is no extension to the general purpose registers. The vector instructions have many new attributes for masked operations, type conversion, broadcast, permutation, cache eviction hint, rounding mode, and suppression of exceptions in addition to the primary function of each instruction.
The first application of this new instruction set will be on the new Intel MIC supercomputing platform, but there are rumors that this new instruction set (or at least the major parts of it) will make it into the mainline x86 ecosystem. The Knights Corner instruction set is carefully designed to be compatible with existing x86 and x64 code. |
Function library update, and more - Agner - 2011-08-04
Disassembler support for Knights Bridge - Agner - 2012-08-24