Surprising new feature in AMD Ryzen 3000

[alaodudonyl]

Could this effectively be used by the compiler to force the cpu to ensure an address is in cache by the time a final store comes about?

For example;

if you intentionally use the destination address as temporary storage (even if unnecessary),

does it begin fetching the address on first reference,

or will the address be brought into L1 only when the core sees a need to write back to cache
(perhaps on a final store in the sequence that can be mirrored)?

[agner]

No. It is using temporary registers inside the CPU. It is not using the cache.