It’s not hard for sure, but still expensive. That’s what AMD was talking about when claimed ‘area-efficient implementation’ on official presentation.
Not entirely true, AMD changed composition of FPU blocks, you can look on die shots (https://www.overclockers.ua/cpu/amd-zen ... -zen-4.jpg). Not something you will usually see in Intel core for comparison.Zen4 is largely the same as Zen3
I think that AMD was forced to change composition of FPU blocks in order to implement AVX-512; yet they wasn’t able to make registers 512-bit wide without inflating core size.