Agner's CPU blog

AMD has since released their optimization guide for Zen4. And it says: The floating point unit supports AVX-512 with 512-bit macro ops and 512-bit storage in the register file. Because the data paths are 256 bits wide, the scheduler uses two consecutive cycles to issue a 512-bit operation. The peak ...

Hi Agner. Thanks for all your work! This is Alex, the author of the mersenneforum post. When I started testing the chip back in August, I initially suspected that 512-bit was split onto 2 x 256-bit pipes simultaneously on the same cycle. But after some further testing, I actually ruled that out. The...