Agner's CPU blog

Cache lines are typically 512-bit on current x86 CPUs. Thanks for correction. James Reinders from Intel mentioned that implementation of AVX wider than cache line would be considerably more challenging. So 512-bit is the long-term boundary then, which means my initial critisism is less valid. many ...

I don't see why AMD (assuming they adopt FP16) would choose not to support it. AVX10.2 doesn't seem to change all that much over AVX10.1, so it doesn't sound like much of a burden on AMD. Agner had mentioned decoder complexity issues. In Zen5, according to rumors, one of AMD focuses is on wider dec...

Intel has announced several new x86-64 instruction set expansions: AVX10 (AVX10.1 and AVX10.2) and completely new APX. The converged AVX10 ISA will include "AVX-512 vector instructions with an AVX512VL feature flag, a maximum vector register length of 256 bits, as well as eight 32-bit mask registers...

Widening the register file to 512-bit probably isn't that complicated. It’s not hard for sure, but still expensive. That’s what AMD was talking about when claimed ‘area-efficient implementation’ on official presentation. Zen4 is largely the same as Zen3 Not entirely true, AMD changed composition of...

https://www.phoronix.com/review/amd-zen4-avx512 People in the forum theme discussion it mentitiong "AVX-512 predication", like That said, I've long been critical of AVX-512, or at least the aspect of it which involves widening vectors to 512-bit. Other things, like predication and scatter/gather, a...