Agner's CPU blog

STA at port 7 calculates the address for a store. The address can be calculated before the data to store is available. The calculated address is passed back to the scheduler where it waits until STD at port 4 needs it. For example: MOV [RAX+RBX],ECX. Here RAX and RBX go to STA to calculate the addr...

agner wrote: ↑

2021-11-04, 15:42:24

Why do you care? NetBurst is long dead.

Yes, it is. I am a newbie so my question was just to understand correctly how thing actually works.

Hi, reading your "The microarchitecture of Intel, AMD and VIA CPUs" latest update 2021-08-17, I would like to ask a question about section 5.4. Starting from table 5.3 pag 55 it seems to me that memory load μops have to go on port 2 (single-speed load execution unit) and not on port 0 as said in the...

Hi Agner, I'm a newby on this topic and reading your very interesting 'The microarchitecture of Intel, AMD, and VIA CPUs' last update 2021-08-17 I came with some questions. From Figure 6.1 pag 71, as far as I can tell, 'ROB wb' block writes-back the result of each executed uop into PRF (Permanent Re...