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Test results for Broadwell and Skylake
Author:  Date: 2017-06-20 14:37
Adding on to my previous comment, the point is that otherwise than some ambiguous decoding scheme for AVX-512 (1 512-bit uOp vs 2 256-bit uOps), which would be entirely dependant on efficiently monitoring which ports (Combined Port "0+1" or Port 5) would be available sooner,or it would look more like a Pentium M/Core multiple-port-single-execution-unit scheme (i.e. where some instructions can be dispatched through multiple ports but share some common execution units). The "Combined Port 0+1" concept would be very similar to the Pentium M/Core scheme, which as stated in Agner's manuals can lead to some performance issues when mixing Dual-port (combined) agains Singe-port instructions, mainly when the shared execution units are used.

Or there is even one last option (but I bet higly unlikely too) : Only one of the 256-bit units (maybe Port 0) being promoted to 512-bit on the lower-end model and both on 512-bit for the higher end models.

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