Agner wrote:
Jorcy Neto wrote:
Maybe, since that AVX512 behaves much like an
alias
for the original IMCI ISA, the timing measuraments
for
KNL's VPUs (except for the doubled throughput)
would't
differ much from those from the KNC VPU.
Knights Landing is expected to be much
better than Knights Corner. It has a very different
microarchitecture.
Indeed, the tighter integration of the VPUs with the Silvermont core frontend will improve on the overall pipeline latency, however, few details were disclosed about the VPU itself. I was also wondering about legacy SIMD performance as only a single VPU is used, opposed to the typical Port 0 + Port 1 configuration on maistream Xeon processors (NHM/SNB//HSW/SKL).www.hotchips.org/wp-content/uploads/hc_archives/hc27/HC27.25-Tuesday-Epub/HC27.25.70-Processors-Epub/HC27.25.710-Knights-Landing-Sodani-Intel.pdf |
Future instruction set: AVX-512 new - Agner - 2013-10-09
Future instruction set: AVX-512 new - Agner - 2013-10-26