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stack ISA versus long vectors

Author: Agner

Date: 2016-04-20 00:08

Hubert Lamontagne wrote:

If you need a second accumulator, that means that your calculations has two branches to it (either from a split or a join), which means it has some parallelism to it

OK, I see.

that's not too hard to do if the vector lengths are in the normal register file, and the SIMD unit is running late compared to the scalar integer unit. Maybe you could have multiple swizzles with different granularities and delay times - like a 1 byte granularity scramble, and then maybe a 4 byte scramble, 16 byte scramble, a 64 byte scramble... Maybe the cpu could look in the swizzle data and figure out how many 0 bits there are and use the coarsest correct granularity.

That's indeed very close to what I have in mind. A permute instruction will have the granularity given by the operand type, one vector output, two vector inputs for input data and indexes, and then a "block size" given by an integer register. For example, if the block size is 16 bytes then data can only be moved within each 16-bytes block of the vector. There has to be a maximum block size anyway because the complexity of the circuit grows with the square of the block size and the latency also grows with the block size. The maximum block size may be implementation dependent and it may be smaller for low granularities.

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