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Do we need instructions with two outputs?
Author: Agner Date: 2016-04-04 08:50
Joe Duarte wrote:
Does an ISA really need to specify the number of architectural registers? What would the implications be of not doing so, and having an infinite number of architectural registers like LLVM's IR?
What do you mean? If we have 1023 virtual registers like LLVM then we need 10 bits in the opcode for each register. Or do you want a rolling register stack? Then we have a problem when the register stack overflows. That would be quite wasteful if the overflow happens in the innermost loop.

Might it be useful to also have an unspecified register – call it Rx – that basically tells the CPU "give me whatever register you have – I don't care which one".
All of the registers behave like that in a superscalar processor. You ask for a particular architectural register and you get a random physical register - you don't even know which one you have got.

Hubert Lamontagne wrote:

then your SP is not 8-byte aligned anymore for 64bit integer and floating-point value. So you must save the vector size word to 0x01FE0 instead, with some extra padding (and the CPU either stores the amount of padding in the vector size word, or recalculates the amount of padding from SP alignment and vector size when reloading the vector).
Yes, this is a complication. I want to handle it in software without any complex instructions. If the size of the saved register image is not guaranteed to be a multiple of the stack word size then I would first calculate the amount of space needed for all the vector registers I want to save, then save the stack pointer to another register, then subtract the necessary size from the stack pointer, then align the stack by 8 ( AND SP,-8 ), then use a temporary register as pointer to the save area, and then save the registers, incrementing the pointer each time. The restore process is easier. There is no problem with saving registers during a task switch because you have a pre-allocated space that is big enough to cover all cases.

The alternative is to give the saved image of each register a size that is a multiple of the stack word size. This will make it easier to spill registers on the stack at the cost of using more space. It will make it simpler for the compiler and also easier for the hardware because of the better alignment. The cost is that it uses more cache space, which is probably more expensive than the extra instructions. If all vector registers are unused, then we will need only one or two bytes for saving each with the first method, versus eight bytes with the second method.

It is difficult to weigh the costs/benefits of these two solutions against each other, but you are right that the first method is very complicated.

Generally, 8-bit and 16-bit vector multiplications are provided in SIMD instruction sets to do stuff like movie decoding and software rendering
x86 does not have a complete set of vector multiply instructions. NEON has 8, 16, and 32 bits. I don't see what you would you need 8-bit vector multiply for?
 
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