Agner`s CPU blog

Agner, why 32 registers? That's an old norm, and thus seems somewhat arbitrary. Is there good empirical research on optimal register count for general purpose modern and foreseeable computing? All I've seen is stuff like this, focused on embedded systems: arxiv.org/ftp/arxiv/papers/1205/1205.1871.pdf By their measures, 80 registers looks good, but it doesn't make a big difference. I don't know if their method is valid, though, since it's not my field. 32 registers seems a bit low in your case since they serve as unified integer/float registers.

Papers I've read recently that you might find interesting:

1. The Idempotent Architecture, which eliminates recovery from mis-speculation. research.cs.wisc.edu/vertical/papers/2011/micro11-idem.pdf

2. ISA extension for hashing, with huge speedups: www.adms-conf.org/2014/adms14_arnold.pdf

3. Logarithmic number system processor as alternative to floating point unit: https://www.ece.ucsb.edu/~parhami/pubs_folder/parh13-asilo-log-arith-as-alt-to-flp.pdf

I like that you're proposing real progress in ISAs. I've been so disappointed in the laziness and lack of innovation in the industry with respect to instruction set architectures, operating systems, and systems programming languages. We've been in an x86, POSIX/Windows, and C rut for a very long time.

John Regehr had some interesting thoughts about what instructions we'd *discover* if we started from first principles and generated optimal instruction sets based on some starting assumptions about what humans need computers to do: blog.regehr.org/archives/669

Regarding your variable vector size, I wonder also about variable data bit-length. The classic doubling values of 8, 16, 32, 64, 128-bit, etc. seem arbitrary to me, and I wonder if a careful empirical investigation might tell us to use different sizes. Or perhaps variable bit lengths could be implemented as easily as variable vector sizes (which usually specify only a couple of allowed field lengths). I don't know what the processor hardware engineering implications of this are. We might discover an energy and performance sweet spot of, say, 24-bit integers or 40-bit floats for lots of applications, for example.