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Proposal for an ideal extensible instruction set
Author: Agner Date: 2016-03-08 02:11
Joe Duarte wrote:
what do you think about a transport-triggered architecture? Could your framework benefit from elements of a TTA? Instruction and code size could be reduced if certain registers automatically squared their contents, for example, or if designated pairs of registers automatically summed their contents. There are many possibilities. (Is there already an incrementer (by 1) register in existing architectures?
A full transport-triggered architecture, as defined by Wikipedia, is very dependent on timing; and the software needs to be recompiled for different CPUs with different latencies in the execution units. I don't see how it can handle out-of-order execution. I think the explicit parallelism will suffer every time there is a cache miss. Your idea is not as radical as this, but it will be very application specific. You cannot use a register that is tied to a specific ALU function in applications that don't need this function. Instructions with read and increment pointer are available in many architectures.

Hard-coded constants like pi etc. are available for the x87-style floating point registers in x86 processors, but these registers are now mainly obsolete and replaced by the vector registers, which don't have this feature. Apparently, the advantage was too small. My proposed instruction set allows immediate floating point constants of both single and double precision. I think this will serve the same need.

 
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