Agner`s CPU blog

Regarding your proposal, what do you think about a transport-triggered architecture? Could your framework benefit from elements of a TTA? Instruction and code size could be reduced if certain registers automatically squared their contents, for example, or if designated pairs of registers automatically summed their contents. There are many possibilities. (Is there already an incrementer (by 1) register in existing architectures? Someone told me there was, but I've not seen it. That would be handy for some loops.)

Relatedly, do you think it would be worthwhile to have certain constants hardcoded into processor? I'm thinking of things like pi, Euler's, sqrt(2), and others. The actual constants to include would be best determined empirically, based on which are most used by programs in this era. Might there be useful speed-ups if a given register multiplied its contents by pi, for example? I have no idea what the physical engineering in the silicon would entail -- perhaps TTAs present difficulties?

Cheers,

Joe Duarte