Agner`s CPU blog

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More ideas
Author: Agner Date: 2016-03-04 11:16
I have an idea that would make it very easy to optimize array loops:

Define an addressing mode [register1 - register2]
Specify vector length (in bytes) in a register. If the specified value is higher than the maximum vector length supported by the processor then the maximum length is used.

Now we can loop through an array in this way:

P = address of array
J = size of array (in bytes)
L = maximum vector length (depends on processor)
X = a vector register
P += J;   // point to end of array
while (J > 0) {
   X = whatever_operation[P-J]{vectorlength J}
   J -= L
}
Here, J has the triple function of loop counter, array index, and vector length. The array size does not have to be a multiple of the vector size: The last iteration of the loop will automatically use a lower vector length if required, and no extra instructions are required to calculate the remaining size. We have completely got rid of the extra code that is typically needed to handle the remaining array elements when the size is not a multiple of the vector length. The code will work optimally on different processors with different maximum vector lengths. There is no need to recompile the code when a new processor with a different vector length appears on the market. Obviously, we can read and write any number of arrays inside the loop, using the same method.

If we don't want to have too many different addressing modes, we can maybe ditch the addressing mode with a scaled index register, assuming that the above method will be used for most loops.

And one more proposal. There is a trend to add more and more feature bits to instruction codes, such as rounding mode, exception control, broadcasting, permutation, shifting, zeroing. This makes instruction codes longer, and it is a waste of code cache size because most of these bits are rarely used. I will propose to put some of these extra feature bits into a register. I have already specified a predicate/mask register in my initial proposal. The extra feature bits will be specified in the same register. Now, we will have only one "enable-features" bit in the instruction code, which enables the extra feature bits in the register. If the "enable-features" bit is zero then all but the predicate/mask bit in the register are ignored.

All unused bits in the features/predicate/mask register are reserved for future use, and must be zero.

Some of the bits in the features/predicate/mask register can be output bits. They can be used for flags (carry, zero, sign, overflow) and accumulating error flags as I proposed in a previous post. The output bits will be unchanged when the "enable-features" bit is zero in order to save a register renaming.

Only features that influence the scheduler and renamer need to be hard-coded into the instruction. Some of the feature bits will not be available for vectors with 8-bit granularity if we don't have enough bits.

 
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