Agner`s CPU blog

If you have, for example, 8B - 2B - 8B, then the second 8B instruction will be misaligned, and the advantage disappears.

I think what we must worry is not only explicit NOPs above, but also implicit unused bits in a instruction.
MIPS-I has 4 fields of 5 bit width for each instruction.
But because of 3 operands architecture, it tends to use only 3 fields leaving 1 field unused.
In my proposal, your 12B instructions have to bloat till 16B, which imply wasting 4B.
According to data compression theory, as predictable these bits is, they holds as less information.
I guess this is a reason why RISCs have lower code density.
It's the trade-off between density and fetch speed of code.
Also from the theory, as we stuff more information in bits, these bits are less predictable = more randomized.
The nightmare of x86 random format might be a proof of high code compression ability.

My understanding for "extensible instruction set" is how to keep old instruction set in the future which is new instruction set we are designing today.
Like you, I also can't imagine the day when 32bit alignment is too small.
But Intel also could not too, and they supposed 8bit alignment is enough, resulting today's nightmare.
So I think we must not imagine enough scale of alignment.
Exponential size is scale-free like fractal.