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Proposal for an ideal extensible instruction set
Author: Agner Date: 2016-02-25 02:13
Agner wrote:
We could add two more flags bits which are accumulating, i.e. the signed and unsigned overflow condition is ORed with the previous value of the flag bit. The program can then check these accumulating overflow flags after a series of instructions.
I wonder if we can get rid of the floating point control word and floating point exceptions with this method.

First, the rounding mode should be specified in the instruction that needs it, not in a global control word. Only few instructions actually need a specified rounding mode, most importantly float to integer conversion. In the rare case where you need a specified rounding mode for addition, multiplication, etc. you will have to use a long version of the instruction with all the option bits.

Floating point errors can be detected in most cases by the INF and NAN propagation mechanism. In the cases where a more detailed error detection is needed, we will specify a combined predication/flags register in the instruction. Bit zero of this register is the predicate. A few more bits are the traditional flags: zero, carry, sign, overflow. And then I want to add a few accumulating error bits which indicate the error condition ORed with the previous value of the same bit. This mechanism also works with vectors, where the flags register is a vector register.

The advantage of this proposal is that we get rid of the floating point control/status register and floating point exceptions. The disadvantage is that we get an extra input and output dependence when a predication/mask/flags register is specified.

 
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