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Proposal for an ideal extensible instruction set
Author: Agner Date: 2016-02-21 02:48
Thank you Hubert for your detailed feedback.

Regarding 16-bit instruction size: I don't think 16-bit is the optimal instruction word size for larger systems, and Moore's law is still making systems larger (it may slow down a little, but it hasn't stopped yet). A 16-bit instruction size means small immediate constants and small address offsets with odd sizes. Most memory addressing should be relative to the instruction pointer or the stack pointer. Using a double-size instruction (2*16 bits), you have 16 bits for address offset. This will give overflow during relocation in the linker or loader if the combined size of code + static data exceeds 32 kbytes (the offset is signed). Relocation overflows happened quite often in the old DOS days, and applications haven't become smaller since then. Most PC applications today are bigger than 32 kbytes, so you need 32 bit address offsets (or ugly memory segmenting). With 16-bit instruction words, you will need at least 5 instruction words for all instructions that access static memory. This means complicated instruction-length decoding. This is one of the reasons for my proposed compromise of a 32-bit instruction word size, and allowing two tiny instructions in a 32-bit instruction word.

Load/store multiple registers instruction: I am imagining that this instruction will be decoded into multiple micro-ops. The only purpose is to save code space.

Add with carry: Your proposal removes the carry output but not the carry input. It will be very complicated if you also remove the carry input: add A+B, generate carry out, add carry in, generate another carry out, add the two carry outs. This is 5 instructions instead of one. Add-with-carry is typically used in high precision math with long chains of add-with-carry. The latency of such a chain will be much longer if you don't have an ADC instruction. Most contemporary instruction sets have two outputs anyway: target register and flags.

Separate register files: My proposal does not have separate registers for integer and floating point - it has separate registers for scalars and vectors. Both can handle integer and floating point. Do you want to split it into four register sets: integer scalar, float scalar, integer vector, float vector? This will require a lot of cross couplings and extra instructions for converting between these. I think that I have more focus on vector instructions (SIMD) than you have. Performance-critical applications are increasingly using vector instructions because this is an efficient way to boost performance. I agree that typical non-vector code has few couplings between integer registers and floating point registers, except for address pointers. But vectorized software has more such couplings, especially for masks, but also manipulation of sign bits etc. Many instructions are the same for integer vectors and floating point vectors, as I have argued before: move, broadcast, blend, permute, gather, scatter.

Predicated instructions: I agree that conditional jumps are faster than predicated instructions if the jump is predicted correctly (but good branch prediction is very expensive in terms of hardware and power consumption). I included predication mainly for the sake of orthogonality between scalar and vector instructions. Masking is indispensable in vector code because you cannot make branches on a per-element basis. Predication is the scalar equivalent of vector masking.

8-bit and 16-bit ALU instructions: These are necessary in vector code, and so they are automatically included in scalar code as well. It would be a waste of power to use 64-bit ALU instructions for everything.

2*ALU instructions: Good idea. We already have multiply-and-add instructions. Double add instructions and shift-and-add instructions would be quite useful as well. Most x86 compilers are actually doing all kind of tricks with the LEA instruction (intended for address calculation) for doing two or three things with one instruction.

Exceptions: Yes, exceptions is a bad thing. It requires a lot of complicated machinery in both hardware and software. We can avoid the need for floating point exceptions by propagating INF and NAN values from the point of error to the final result of a calculation. The IEEE floating point standard includes an error code in the NAN which is propagated through the calculations. (The error codes should be OR'ed when two NAN values are added. Unfortunately, many microprocessors today fail to do this and only propagate one of the two NAN codes). It would be nice to have a mechanism for detecting errors in integer code as well, but I don't know how to do it. Most systems today generate an exception for integer division overflow, but not for overflow in integer addition and multiplication. This is illogical. We also need an efficient way of detecting if an array index is out of bounds.

 
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