BTW, AnandTech mention live VM migration as another example of where x86 CPU extensions can cause a lot of hassle.
You have to often fiddle with CPU masks to migrate across CPU generations, and even then it isn't always possible to mask all features..
But even more important is the effect on cross-vendor live VM migrations.
In fact, Red Hat and AMD demoed cross-vendor live VM migration back in 2008:
linux.slashdot.org/article.pl?sid=08/11/07/1535235
It isn't mentioned very often in the discussions, but it is important.
You see, back before AMD adopted AVX, AMD was going with SSE5 (in fact SSE4a is available already on today's Family 10h AMD processors) and Intel was going with AVX.
If cross-vendor live VM migration was to work properly, the VM would have to be crippled all the way back down to SSE3.
Even now, the FMA4 vs FMA3 wars means that VMs that have to migrate between Intel Ivy Bridge processors and AMD Bulldozer processors would have no access to FMA at all. |
Stop the instruction set war new - Agner Fog - 2009-12-05
The instruction set war's effect on virtualization - Yuhong Bao - 2009-12-28