Agner`s CPU blog

I do not remember now who made this observation first, because I have read it somewhere, but I agree with it.

The main advantage of the classic vector computers is that they had a vector length register, which determined the size of the performed operation, and that length could have any value between 0 and the maximum length of the vector registers, i.e. it was not restricted to powers of two, like in the instruction field from your proposal or like in AVX, Neon etc.

This has the advantage that it simplifies considerably the code that must deal with the initial or final parts of the arrays whose sizes are not a multiple of the size of a vector register or which do not have a correct alignment.

For AVX-512 and longer vector registers it is likely that the code dealing with all the possible cases of lengths and alignments will be much larger than the code for the main loop, and it will increase in geometric progression for each new maximum vector length.

With a vector length register, this extra code will be much smaller and its size will remain unchanged when the size of the vector registers will be increased.

Unlike the separate scalar & vector registers, which I believe to be mandatory from the perspective of the operating system & ISRs, and which is a feature with minimal influence upon your proposed instruction encoding, the use of one or more vector length registers (maybe the registers r8 to r16 , like the use of r0 to r7 for predicate registers) might require more significant changes in your proposal for instruction encoding, e.g. the use of those 3 bits to specify a vector length register instead of a length, so you must assess if you believe that it is worth it.

Like I said this is not my proposal and I do not remember right now where I have read it, but I found its argumentation compelling.