Agner`s CPU blog

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Proposal for an ideal extensible instruction set
Author:  Date: 2016-01-04 05:57
While I fully agree with the stated purpose of RISC-V, I strongly disagree with some of their choices for instruction encoding, especially with their addressing modes.

The features proposed by Agner are much closer to what I would consider a good ISA, and I have a lot of experience in programming in assembly language for a huge number of different ISA's from antiquities like IBM System/360, PDP 11, Intel 8080 or Motorola 6800 up to current ISA's, like Intel/AMD, IBM POWER or ARM.

I only want to comment about the addressing modes, because many other ISA proposals, including RISC-V, do not seem to have any clue about how they are used in real programs.

There are only 2 possible choices for a set of addressing modes that would allow writing a loop with a minimum number of instructions.

The first possible choice coincides with the subset of the VAX 11 addressing modes implemented in Intel 80386, which, like in the Agner proposal, allows addresses with 3 components, a base register, a scaled index register and an offset included in the instruction.

This choice of addressing modes was probably the only feature of the Intel 80386 ISA that was better than in the earlier Motorola MC68020. Motorola has chosen to implement almost all the addressing modes of VAX 11, not only the subset chosen by Intel, but the addressing modes omitted by Intel were not really useful, so eventually even Motorola abandoned them in the ColdFire processors.

The second possible choice for the set of addressing modes appeared initially (around 1980) in one of the IBM RISC processors that were later developed into IBM POWER. This choice was also adopted by ARM, after it was published by IBM at one of the early RISC conferences.

This second choice is to allow addressing modes with only 2 components, a base register and an offset either in a register or in the instruction, but to allow updating the base register with the computed address.

I believe that the IBM choice is somewhat better, but both choices are acceptable. Any other set of addressing modes, e.g. RISC-V, is wrong, because it requires in almost all loops the insertion of extra instructions for updating the addressing registers.

Even if the hardware could execute the extra instructions in parallel, there would be a waste of resources anyway, because the extra instructions would occupy decoder slots and space in the instruction caches.

The IBM choice has the advantage that it does not require a second address adder and a shifter for scaling, but the disadvantage that it requires an extra write port into the register file.

From a software point of view, the IBM choice has the advantage that it is universal, i.e. it can be applied to any loop, while the Intel 80386 choice can be applied only to loops where the data structures have been chosen carefully. The reason is that, in order to avoid extra address updating instructions, the scaled index register must be the loop counter, and this, together with the limited set of values that may scale the index, forces that the ratios between the sizes of the elements of the arrays accessed during the loop must belong to the set of scale values (1, 2, 4, or 8 for Intel/AMD).

Nevertheless, these constraints for data layout are acceptable in most cases.

In order to evaluate which choice is cheaper from a hardware point of view, it is necessary to know exactly the technology used for implementation. If a second write port would be needed anyway for the register file due to other reasons, then the IBM choice would be certainly cheaper.

So, in conclusion, the set of addressing modes proposed by Agner is certainly much better than that of RISC-V.

I also completely agree with the use of a set of general registers instead of a dedicated flag register.

There should also be a complete set of instructions that would allow the writing of efficient programs for multiple precision computation, e.g. the GMP library.

Despite the ugliness of most of the legacy part of the Intel ISA, during the last 10 years Intel has improved continuously the support for multiple precision computation, leaving all the competition far behind.

All the RISC ISA's had traditionally bad support for multiple precision computation, even if that had nothing to do with the RISC principles. Even in the old days, when the need for encryption was not yet widely recognized, there were some users, like myself, who executed frequently that kind of instructions for scientific and technical applications.

 
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