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FP pipelines on Intel's Haswell core
Author:  Date: 2015-09-24 20:54
John D. McCalpin wrote:
[...] Given the 3-cycle latency of FP Add and the 5-cycle latency of both FP Multiply and FP Fused-Multiply-Add, it seems reasonable to speculate that Intel only wanted to add the extra complexity of an "early out" mechanism on one execution port (Port 1). With no need to change the latency, it is trivial to support an isolated Multiply on either Multiply-Add pipeline. Also note that the other FP execution port (Port 0) is already burdened with the logic for FP divides, which is fairly extensive. [...]
I guess Intel has decided as well to move the Integer SIMD Multiplier from Port 1, back to Port 0, to alleviate some of the SIMD stress on it, as it (Port 1) still keeps the sole "pure" FP-Add execution unit, even on a cost of agreggating a higher complexity (and more Integer stress/workload) back on Port 0.
Interestingly , keeping the Integer SIMD Multipler within the same Port as the Divider in the P6 family, is a thing that hasn't been seen since the Pentium III/Pentium M days.
 
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