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Test results for Intel's Sandy Bridge processor

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Date: 2015-08-24 11:22

My test code measured the elapsed TSC time (using RDTSCP) and used the performance counters to measure Unhalted Core Cycles and Unhalted Reference Cycles (with inline RDPMC instructions). The difference between TSC cycles and Unhalted Reference Cycles gives the number of halted cycles, and the ratio of Unhalted Core Cycles to Unhalted Reference Cycles gives the average core frequency while not halted (relative to the nominal frequency). This data is sufficient to clearly distinguish low-frequency operation from operation in a degraded performance mode. It might not be enough to identify operation with T-state throttling -- I have never tried to use that feature....

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