Agner`s CPU blog

I added an outer loop with a (non-256-bit) "spinner" to see how long it takes for the processor to revert to initial behavior. If the spinner between outer loop iterations was less than 1 millisecond, the subsequent inner iterations ran at full speed. If the spinner between outer loop iterations was more than 1 millisecond, the subsequent inner iterations showed the behavior above.

This behavior occurs even if the core frequency is bound any of the available frequencies (except perhaps the lowest frequency -- I need to go back and double-check those results). Performance counters showed that the core was running at the requested frequency in each case (comparing actual and reference cycles gave the expected ratio).
There are no kernel cycles, even during the transition.
The performance counters for micro-ops dispatched to the various ports show only very minor differences between the "warm-up" and "normal" cycles.
I could not find *any* performance counters (other than cycles) that could distinguish between the 1/4-speed "warm-up" and "normal" operations (but I have not tried all of them).

So this looks like a very low-level emulation of the 256-bit pipeline by forcing everything through the bottom 128-bit pipe, with a remarkably slow transition when the upper 128-bit pipe is enabled. Perhaps the current draw is so large that the chip has to wait for the voltages to settle, even with no frequency change?

I did not look for evidence of the overhead of the transition in the other direction -- I assume it will be much quicker to turn off the upper 128-bit FP pipe than to turn it on.