| My guess is that CMOV is already taking care of this well enough. Conditional prefixes would take too much space and bloat the code - hitting bottlenecks in decoders and icache. A few CMOVs at the end of an if-else-endif block take less space than a prefix before each instruction inside. Also notice that for some reason Intel cores seem to be limited to 2 inputs per decoded µop. Adding an extra dependency (the condition register) would necessitate adding a µop to most prefixed instructions. Not good. Speaking of which, this would require keeping the condition in a register at all times. Most x86 integer instructions modify the flags, so you can't keep the condition there. The x86 arch isn't exactly overflowing with registers, to waste 'em like that. BTW, other CPU architectures are turning away from condition codes recently, for similar reasons. ARM has got rid of them in newer ISA versions (Thumb(-2) and ARMv8), replacing them with an "if-then-else" instruction. Maybe we will someday see a similar instruction in x86. | 
Optimization manuals updated new - Agner - 2013-09-04
Optimization manuals updated new - Agner - 2014-02-19
