Agner`s CPU blog

The optimization manuals at www.agner.org/optimize/#manuals have now been updated. The most important additions are:

• AMD Piledriver and Jaguar processors are now described in the microarchitecture manual and the instruction tables.
• Intel Ivy Bridge and Haswell processors are now described in the microarchitecture manual and the instruction tables.
• The micro-op cache of Intel processors is analyzed in more detail
• The assembly manual has more information on the AVX2 instruction set.
• The C++ manual describes the use of my vector classes for writing parallel code.

Some interesting test results for the newly tested processors:

AMD Piledriver

• Similar microarchitecture to Bulldozer
• Supports fused multiply-and-add instructions in both the FMA3 and FMA4 form. FMA3 is compatible with Intel processors. See Wikipedia for a discussion of the incompatibility between these instruction sets.
• The throughput of FMA3 instructions is only half as much as the throughput of FMA4 instructions, even though they are doing exactly the same calculations.
• Memory writes with the 256-bit AVX registers are exceptionally slow. The measured throughput is 5 - 6 times slower than on the previous model (Bulldozer), and 8 - 9 times slower than two 128-bit writes. No explanation for this has been found. This design flaw is likelty to negate any advantage of using the AVX instruction set.
• The problems with cache performance on the Bulldozer seem to have been fixed in the Piledriver

AMD Jaguar

• Similar microarchitecture to Bobcat
• Supports the AVX instruction set
• Does not support AMD's 3DNow and XOP instruction sets. This is OK with me since few programmers would care to make a special version of their code specifically for AMD processors.
• The vector execution units are doubled in size from 64 bits in Bobcat to 128 bits in Jaguar. The throughput of vector instructions is doubled. Floating point scalar (non-vector) performance was quite good already on the Bobcat and is unchanged on the Jaguar.
• Load and store units are also doubled from 64 bits to 128 bits.
• Store-to-load forwarding is much faster than on Bobcat
• The prefetch instruction is particularly slow on Jaguar. The throughput is much lower than on other AMD processors.
• Integer division is improved
• Register moves with vector registers are eliminated if the register is known by the processor to be zero. Register moves are not eliminated if the value of the register is unknown. This seems to indicate that registers are not allocated if they are known to be zero.
• The VMASKMOVPS instruction with a memory source operand takes more than 300 clock cycles on the Jaguar when the mask is zero, in which case the instruction should do nothing. This appears to be a design flaw. This instruction is not very common, though.

Intel Ivy Bridge

• Similar microarchitecture to Sandy Bridge
• Can eliminate register-to-register moves by renaming the target register
• Problem with decoding long NOPs in Sandy Bridge has been fixed
• Some execution units have been moved to a different port
• Handling of partial registers is improved
• The prefetch instructions are particularly slow on Ivy Bridge. The throughput is much lower than on other Intel processors.
• Store-to-load forwarding is generally good, but in some unfortunate cases of an unaligned 256-bit read after a smaller write, there is an unusually large delay of more than 200 clock cycles.

Intel Haswell

• Supports the new AVX2 instruction set which allows integer vectors of 256 bits and gather instructions
• Supports fused multiply-and-add instructions of the FMA3 type
• The cache bandwidth is doubled to 256 bits. It can do two reads and one write per clock cycle.
• Cache bank conflicts have been removed
• The number of read and write buffers, register files, reorder buffer and reservation station are all bigger than in previous processors
• There are more execution units and one more execution port than on previous processors. This makes a throughput of four instructions per clock cycle quite realistic in many cases.
• The throughput for not-taken branches is doubled to two not-taken branches per clock cycle, including fused branch instructions. The throughput for taken branches is largely unchanged.
• There are two execution units for floating point multiplication and for fused multiply-and-add, but only one execution unit for floating point addition. This design appears to be suboptimal since floating point code typically contains more additions than multiplications. But at least it enables Intel to boast a floating point performance of 32 FLOPS per clock cycle.
• The fused multiply-and-add operation is the first case in the history of Intel processors of micro-ops having more than two input dependencies. Other instructions with more than two input dependencies are still split into two micro-ops, though. AMD processors don't have this limitation.
• The delays for moving data between different execution units is smaller than on previous Intel processors in many cases.

The optimization manuals at www.agner.org/optimize/#manuals have now been updated with test of the AMD Steamroller microprocessor.

There are also minor additions regarding the forthcoming AVX-512 instruction set.

I have not tested the Intel Silvermont/Bay Trail processor yet because the test machine I have access to cannot run Linux, and the kind of tests that I want to do are very difficult to do under Windows.

Test results for AMD Steamroller

• Similar microarchitecture to Bulldozer and Piledriver
• Has one instruction decoder per thread, where previous designs shared a decoder between two threads. This removes a potential bottleneck.
• Instruction fetch is still shared between two threads. This is a likely bottleneck.
• Instruction cache increased by 50%
• New loop buffer can store at least 32 decoded instructions. The exact size is not known
• Improved throughput for level-2 cache write
• Store forwarding improved. Supports small read after bigger write
• Floating point / vector unit redesigned with three pipes where previous designs had four pipes
• Maximum throughput is four instructions per clock when integer and vector instructions are mixed
• Floating point division improved
• No penalty for floating point denormal and underflow results
• Some performance flaws in Piledriver have been fixed. Most importantly, 256-bit stores are now performing well
• A new performance flaw has been added, though. Floating point vector addition has lower throughput than expected
• Supports AVX, but not AVX2

I noticed that the Intel documentation at https://software.intel.com/sites/landingpage/IntrinsicsGuide/ shows "VPTEST ymm, ymm" as having a latency of 4 cycles on Haswell, up from 2 on Sandy and Ivy Bridge. They also list "PTEST xmm, xmm" as having a latency of 2 on all platforms.

Your current guide shows a latency of 1 for "PTEST x,x" on Sandy Bridge, and 2 for "PTEST v,v" on Haswell. Are you confident in these measurements, or is it possible that the Intel guide is correct here? Or is this just a terminology difference between PTEST and VPTEST?

Thanks!

Intel's old low-power processor named Atom has now finally got a major update after several years in service. The new design called Silvermont is a small low-power processor intended mainly for mobile devices and as a competitor for ARM machines.

The Silvermont still contains traces of the old Atom design, but almost everything has been improved or redesigned. The chip has one or more units with two cores each. The two cores in a unit share the same level-2 cache but they have separate execution resources. Thus, there is no competition for execution resources between threads.

The Silvermont supports the SSE4.2 instruction set, but not AVX and AVX2. It has a throughput of two instructions per clock cycle. There are two execution pipes for integer instructions, two for floating point and vector instructions, and one for memory read and write. Internal buses and execution units are 128 bits wide. Most execution units are pipelined, but some operations are staying in the same pipeline stage for two (rarely four) clock cycles in the cases of large data sizes or high precision.

The high end processors from Intel and AMD have powerful capabilities for out-of-order execution, while the old Atom executes all instructions in program order. The Silvermont is a compromise between these two. It has some out-of-order execution, but not much. Integer instructions in general purpose registers can execute out of order with a depth of at most eight instructions. Floating point and vector instructions cannot execute out of order with other instructions in the same of the two floating point pipelines. There is full register renaming.

The cache size is reasonable: 32kB level-1 code, 24kB level-1 data, 1MB level-2. Cache latencies were 3 and 19 clock cycles in my measurements, and the cache performance is generally good.

The whole design seems well proportioned with reasonable capacities for a low-power chip in all stages of the pipeline - except for one very big bottleneck: the decoders. Simple instructions can decode at a rate of two instructions per clock cycle, but there are quite a lot of instructions that the decoders cannot handle so smoothly. Instructions that generate more than one micro-operation, as well as instructions with certain combinations of prefixes and escape codes, take four, six or even more clock cycles to decode. In many of my test cases I was unable to determine the latency and throughput of the execution units for certain instructions because the decoders were far behind the execution units. The designers have already removed the common bottleneck of instruction-length decoding by marking instruction boundaries in the code cache (a technique that Intel haven't used since the Pentium MMX seventeen years earlier). It should be possible to remove the unfortunate bottleneck in the decoders without sacrificing too much power consumption. Let's hope that Intel will have solved this problem in the next version of the Silvermont, as well as in the forthcoming Knights Landing coprocessor, which is rumored to be based on the Silvermont architecture.

Other news in my manuals include calling conventions for the forthcoming AVX512 instruction set, and an update on how to circumvent Intel's CPU dispatcher for Intel compiler version 14.

Descriptions of "partial OoO" and other things are here: www.realworldtech.com/silvermont/ . Kanter usually gets such info directly from design team.

There is no penalty for unaligned read or write unless a cache line boundary is crossed.

When do you think Intel could add conditional operation prefix?

Conditional prefixes would take too much space and bloat the code - hitting bottlenecks in decoders and icache. A few CMOVs at the end of an if-else-endif block take less space than a prefix before each instruction inside.

Also notice that for some reason Intel cores seem to be limited to 2 inputs per decoded µop. Adding an extra dependency (the condition register) would necessitate adding a µop to most prefixed instructions. Not good.

Speaking of which, this would require keeping the condition in a register at all times. Most x86 integer instructions modify the flags, so you can't keep the condition there. The x86 arch isn't exactly overflowing with registers, to waste 'em like that.

BTW, other CPU architectures are turning away from condition codes recently, for similar reasons. ARM has got rid of them in newer ISA versions (Thumb(-2) and ARMv8), replacing them with an "if-then-else" instruction. Maybe we will someday see a similar instruction in x86.

It seems the POPCNT instruction has a false dependency on its *output* register on Intel CPUs. At least it does on my Sandy Bridge and on my friend's Haswell. Damn you, Intel!

* There are two execution units for floating point multiplication and for fused multiply-and-add, but only one execution unit for floating point addition. This design appears to be suboptimal since floating point code typically contains more additions than multiplications.

McCalpin's Comments:
0. Definitely agree on the (typical) excess of FP Add over FP multiply operations. The ratios are mostly between 1:1 and 2:1, depending on the application area. I usually assume 1.5:1 in architectural analyses (while keeping in mind that this is a "fuzzy" estimate).
1. Of course one can always expand an FP Add into an FMA to run in the other pipeline. You need a YMM register to hold the dummy "1.0" multiplier values, but in principle it would not be difficult to teach a compiler this trick, along with suitable cost metrics to decide when to employ it.
2. Given the 3-cycle latency of FP Add and the 5-cycle latency of both FP Multiply and FP Fused-Multiply-Add, it seems reasonable to speculate that Intel only wanted to add the extra complexity of an "early out" mechanism on one execution port (Port 1). With no need to change the latency, it is trivial to support an isolated Multiply on either Multiply-Add pipeline. Also note that the other FP execution port (Port 0) is already burdened with the logic for FP divides, which is fairly extensive.

On a related note, the latency and throughput numbers for FP divide on various Intel processors suggest that 128-bit FP divide operations perform two 64-bit divides in parallel. (Presumably taking the same number of iterative steps on both values, even if one could have an "early out".) For AVX on Sandy Bridge, Ivy Bridge, and Haswell the reciprocal throughput for the 256-bit FP divide instructions is twice the value for the 128-bit FP divide instructions. This suggests that only one 128-bit "lane" of the FP unit on Port 0 actually supports FP division, and that 256-bit FP operations are performed internally as a sequence of two 128-bit (2-way parallel) FP divide instructions. You show this in the instruction tables as 1 uop on Port 0 for 128-bit FP divide and 2 uops on Port 0 for 256-bit divide, but I had not seen anyone comment specifically on the absence of FP divide throughput speedup on AVX before, so I thought I would bring it up.

Considering this lack of speedup with 256-bit AVX makes one wonder if the 512-bit FP divide instruction in AVX-512 will support higher throughput, or if they will leave the HW implementation where it is and emphasize the SW-pipelined approach (currently used by Xeon Phi, for example). By the time you get to 8-element vectors, the SW approach is almost certainly faster if you don't have to reach full 0.5 ulp precision.

.. wonder if the 512-bit FP divide instruction in AVX-512 will support higher throughput

[...] Given the 3-cycle latency of FP Add and the 5-cycle latency of both FP Multiply and FP Fused-Multiply-Add, it seems reasonable to speculate that Intel only wanted to add the extra complexity of an "early out" mechanism on one execution port (Port 1). With no need to change the latency, it is trivial to support an isolated Multiply on either Multiply-Add pipeline. Also note that the other FP execution port (Port 0) is already burdened with the logic for FP divides, which is fairly extensive. [...]

I didn't see any mention of this in your optimization manual or microarchitecture docs.

I tested again with store instructions, as that's an example used in your microarch doc, and it seems they can only fuse when 1-reg addressing modes are used. For example,

mov [rsi + 0 + rdi], eax ; produces as many fused as unfused uops.

mov [rsi + 0], eax ; produces 1 fused-domain, 2 unfused-domain uops

I'm doing all my testing on 64bit Linux, on an i5 2500k (SnB). I just tested a 32bit binary, and got the same results, since your example did use 32bit registers. Same result: mov [esi+edi], eax can't micro-fuse. Assembled/linked with:
yasm -f elf32 uop-test.s && ld -m elf_i386 uop-test.o -o 32.uop-test
file(1) says it's a 32bit elf statically linked binary, so I'm pretty sure I did this right. :P

In the Core2/Nehalem section of your architecture guide, you say:
A fused μop can have three input dependencies, while an unfused μop can have only two.

I think this is wrong. I haven't tested Core2 or Nehalem, just SnB, but the SnB/IvB section simply refers back to the Nehalem section without mentioning any caveats. I'm sure it's wrong for SnB. IACA with -arch NHM doesn't show micro-fusion for 2-reg addresses for stores, or ALU ops, so this needs testing on Nehalem hardware, too. (IACA can't analyse for pre-Nehalem arches.)

off-topic: It'd be nice if the microarch doc didn't refer back to how things were somewhat different on older architectures quite as much. It gets to be a problem for micro-op fusion, where SnB refers you back to the Nehalem section AND the P-M section. At least the SnB section doesn't have anything new to add. I think it might be a good idea to have the Nehalem section not refer back to P-M, or at least summarize anything it doesn't say itself, though, since two levels of recursion is pushing it.

That's about the only bad thing I can say about your work, though! Overall, it's an amazing resource. Making each section stand alone would bloat things, and make it less obvious when things were the same for multiple CPUs, so that wouldn't be good, either.

uop micro-fusion on Intel SnB seems to be possible only when it doesn't create uops with more than 2 input dependencies.

Have you tried with FMA instructions?

uop micro-fusion on Intel SnB seems to be possible only when it doesn't create uops with more than 2 input dependencies.

The results show that instructions with three input dependencies are fusing alright and use only a single entry in the micro-operation cache, unless they contain more than 32 bits of address and immediate data. Instructions with more than 32 bits of data are still fusing, but use two entries in the micro-operation cache. It is possible to make instructions with four input dependencies on Haswell and Broadwell, using the fused multiply-and-add instructions. These are still fusing alright and use only a single entry in the micro-operation cache.

Instructions with both rip-relative addressing and immediate data do not fuse.
The results are identical on the four machines tested.

Peter Cordes wrote:

uop micro-fusion on Intel SnB seems to be possible only when it doesn't create uops with more than 2 input dependencies.

I have now tested this on Sandy Bridge, Ivy Bridge, Haswell and Broadwell. I have not had access to test on a Skylake yet.

The results show that instructions with three input dependencies are fusing alright and use only a single entry in the micro-operation cache ...

Our test results disagree. I see a change in the uop perf counters, and an increase in the clock cycles taken, when changing from or eax, [rsi] to or eax, [rsi+rdi]. I didn't try to measure uop-cache slots, just a total cycle count, and fused/unfused uop counts. My full test code, and the Linux perf command I used to get data from the performance counters, is posted on stackoverflow.

Based on Tacit Murky's information that SnB's internal uop format doesn't have room for a micro-fused index register, maybe 2-register addressing modes can still micro-fuse in the uop cache, but not in the pipeline where the ROB tracks them.

Did your test results make an assumption about uops in the uop cache being the same as fused-domain uops in the pipeline?

I re-ran my test after seeing your response, and I'm still sure I'm seeing 2-register source operands NOT micro-fusing. If I'm wrong, can you please have a look and help me figure out what's wrong with my test procedure? I've been using
ocperf.py stat -r4 -e task-clock,cycles,instructions,uops_issued.any,uops_dispatched.thread,uops_retired.all,uops_retired.retire_slots,stalled-cycles-frontend,stalled-cycles-backend ./uop-test

I'm essentially testing fused-domain uops against the 4-wide limit of the pipeline for issuing / retiring 4 fused-domain uops per clock. Some of my fused-domain uops are NOPs, to avoid execution port unfused-domain bottlenecks on SnB.

The results show that instructions with three input dependencies are fusing alright and use only a single entry in the micro-operation cache

I found official confirmation in Intel's optimization manual that we're both right (see Section 2.3.2.4: "Micro-op Queue and the Loop Stream Detector (LSD)"), we were just measuring different things. SnB-family still micro-fuses such instructions in the decoders and uop-cache, but "un-laminates" uops with an indexed addressing mode before the issue/rename stage. The uop format used in the ROB must be different from the format in the uop cache. The unfused-domain scheduler (RS) must still handle uops with indexed addressing modes, because pure loads with complex addressing modes are still a single p23 uop.

Tacit Murky's earlier post says that the un-lamination happens as uops are written to the IDQ, so the loop-buffer size is measured in un-laminated uops.

For the purposes of pipeline width and tight loops, indexed addressing modes don't micro-fuse. The 4-wide issue width is after un-lamination.

For the record, un-laminate is not a normal English word, but delaminate is. I want to put quotes around it every time I type it. >.<

BTW, I updated my answer on StackOverflow with this info.

Any plans to update the manual with skylake information?

The last 3 major core releases have had ~18 months between the release of the first "client" part and the release of the 2-socket server part, so if that schedule is repeated we should see the Skylake Xeon EP in 1H2017. Earlier seems unlikely, since we have not seen the "Broadwell EP" yet. Later is certainly possible, since this is the first time that there has been a major ISA-level difference between the "client" and "server" core.

Besides AVX-512, it is known that those Skylake Xeon processors will have a large number of other improvements, e.g. a new socket with 6 memory channels, possibly the same socket that will be used by Knights Landing.

Knights Landing, the first processor with AVX-512, is rumored to have been delayed until Q3 2016, so it will probably be introduced about a half year earlier than Skylake with AVX-512.

In conclusion, I hope that Agner will not wait to test Skylake until AVX-512 becomes available, because that will not happen any time soon.

From the Intel optimization manual, Skylake does not seem to have any dramatic differences compared to Broadwell & Haswell, unlike the jump between Ivy Bridge & Haswell, or between Nehalem & Sandy Bridge. Nevertheless, a detailed testing might uncover interesting features.

Of the large number of Skylake models already introduced, only one is interesting for myself, Xeon E3-1535M v5, because for servers Broadwell (Xeon D-1540) is a much better option for now.

Xeon E3-1535M v5 will become available in the new models of mobile workstations announced by Lenovo and Dell.

I will buy one ASAP, but it seems that those mobile workstations will be offered only in December or maybe even only in January, where I live.

I will use Linux on it, and, if by that time Skylake would not be tested yet, I could easily offer remote access to it. Nevertheless, there are still 3 months until then, so maybe another kind soul will provide access to Skylake earlier.

You're also missing Excavator and Puma cores on the AMD side. I hope you will get a chance to test those soon!

Right now, the cheapest way to get your hands on a Puma seems to be this barebone. Still kinda pricey though.

Then again - maybe you could buy a whole computer just to make a few tests - and then sell it off? Carrizo laptops are on the market long enough for some used units to be occasionally floating on fleaBay. Should you buy one, you should be able to resell it at minimal (if any) loss.

That shouldn´t be so hard to get :)

www.anandtech.com/show/10009/amd-launches-excavator-on-desktop-the-65w-athlon-x4-845-for-70