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Test results for Intel's Sandy Bridge processor
Author: Agner Date: 2013-08-07 11:11
anon wrote:
But if we change 6 ORs into AND(or other macro-fusable instructions), it drops to 2.5 clocks / 8 instructions. It means that the decoder cannot handle four macro-fusable instructions at the same clock cycle.
I get 2.45 clock on an Ivy Bridge. I get the same for NOT and NEG, which are not fusable. There is nothing the instructions can actually fuse with, though.
 
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