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Test results for Intel's Sandy Bridge processor
Author: anon Date: 2013-08-07 07:19
500 iterations of this code sequence (4,000 instructions, does not fit to uop cache):

or rax, 1
or rdx, 1
or rsi, 1
or rdi, 1
or r8, 1
or r9, 1
movaps xmm0, [r10]
movaps xmm1, [r11]

runs at 2 clocks / 8 instructions (as expected). But if we change 6 ORs into AND(or other macro-fusable instructions), it drops to 2.5 clocks / 8 instructions.

It means that the decoder cannot handle four macro-fusable instructions at the same clock cycle.

 
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